1. Field of the Invention
The present invention relates to a multi-chip package structure. More particularly, the present invention relates to a multi-chip package structure having a plurality of flip chips stacked over a substrate carrier, capable of improving electrical performance of the substrate and reducing area occupation of the multi-chip package.
2. Description of the Related Art
In this information-base society, electronic products have become an indispensable tool serving us in many ways all around the clock. As electronic technologies continue to progress, many multi-functional and fast computing electronic products with a large memory storage capacity have been developed. These products are not only more powerful than the previous generation, but also increasingly light and compact as well. To reduce weight and volume of a package, the concept of integration must be incorporated into the design of integrated circuits. Since the fabrication of integrated circuits with nanometric features is now possible, many functions can be incorporated within a tiny chip.
To increase chip package function without increasing size, semiconductor manufacturers have developed several highly compact type of packages including the multi-chip module, the chip-scale package and the stacked multi-chip package. FIG. 1 is a schematic cross-sectional view of a conventional stacked multi-chip package structure.
As shown in FIG. 1, a conventional stacked multi-chip package 100 comprises a first chip 110, a second chip 120, a substrate 130, a plurality of bumps 140, 142, some insulating material 150 and a plurality of solder balls 160. The first chip 110 has a plurality of bonding pads 112, 116 on an active surface 114. The second chip 120 similarly has a plurality of bonding pads 122 on an active surface 124. The first chip 110 and the second chip 120 are electrically connected through the bumps 140. One end of each bump 140 is bonded to one of the bonding pads 112 of the first chip 110. The other end of the bump 140 is bonded to a corresponding bonding pad 124 on the second chip 120. The active surface 114 of the first chip 110 faces the active surface 124 of the second chip 120. The substrate 130 has a through opening 132 capable of accommodating the entire second chip 120. Furthermore, the substrate 230 has a plurality of bonding pads 134, 135 on an upper surface 136 and a lower surface 137. The bonding pads 134 are positioned around the peripheral region of the opening 132. The first chip 110 and the substrate 130 are joined together through the bumps 142. One end of each bump 142 is bonded to one of the bonding pads 116 of the first chip 110. The other end of the bump 142 is bonded to a corresponding bonding pad 134 of the substrate 130. The solder balls 160 are attached to the respective bonding pads 135 of the substrate 130. The insulating material 150 is deposited within the opening 132 to enclose the bumps 140 and the second chip 120.
In the aforementioned multi-chip package 100, the opening 132 must be fabricated in the substrate 130 to accommodate the second chip 120. Moreover, circuit wires have to be routed around the opening 132, causing the increase of the overall signal transmission length. This setup not only lowers the electrical performance of the substrate 130, but also complicates the manufacturing process and increases the production cost. Meanwhile, the outer perimeter of the substrate 130 has to increase, thus leading to some difficulties in reducing overall size of the multi-chip package 100.